3D TSV Packages Market Segments and Forecast By End-use Industry 2016-2026

Currently, 3D Packaging using Through Silicon Via technology (3D TSV) is one of the hottest topics in the semiconductor ecosystem. 3D TSV is vertical electrical connection (via) passing completely through a silicon wafer or die. These short vertical interconnects are replacing the long interconnects of 2D packaging technologies including wire-bond and flip chips.

Growing demand for high density and multifunctional microelectronics with improved performance, and the reduction of timing delays is currently driving the market for 3D TSV packages. . However, the challenges encountered during assembly and packaging, handling ultrathin semiconductor components in front-end and back-end process owing to its fragility are some of the factors restraining the market growth.

Market Overview:

Several 3D packages, such as System in Package and Chip Stack MCM, are available in the market providing smaller form factor and greater connectivity. The stacked chips are wired together along their edges in these packages. This wiring increases the length and width of the package, thus requiring an extra “interposer” layer between the chips. The new 3D TSV package creates vertical connections through the body of the chips, replacing edge wiring and in turn reducing the extra added length and width.

3D TSV technology allows stacking of LSIs which facilitates manufacturing of smaller products such as wearable devices. , Semiconductor fabricators globally are adopting 3D TSV technology in order to cater to the increasing requirements of functional integration.

Market Dynamics:

Growing demand for innovative chip architectures with improved features such as low power consumption, high aspect ratio, and smaller form factor is driving the market of 3D TSV packages. Additionally, factors such as proliferation in the cloud based applications, robust outlook for the Information & Communication Technologies segment, and persistent developments in the DRAM and smart lighting sectors are further cementing the adoption of 3D TSV packages for fabrication process.

The market is expected to witness potential revenue opportunity mainly due to growth in its application areas such as MEMS, CMOS image sensors, optoelectronics and high end LED solutions. Additionally, 3D TSV packages are expected to gain more traction in its adoption in the DRAM memory domain with the advent of innovative technologies such as HMC (Hybrid Memory Cube) and HBM (High Bandwidth Memory).

Several challenges are encountered while handling this wafer for packaging process as the TSV wafer is thinned down to the thickness of 40-50um. TSV wafers are thinned in order to meet the diverse needs, including temporary adhesion strength, and chemical and thermal stability in the fabrication process. These challenges are constraining the growth of the market and are expected to continue hampering the market growth during the forecast period. Furthermore, 3D TSV assembly process is more complex, compared to traditional flip-chip process which is also one of the primary constraint for this market.

With the up surging demand for improved and advanced electronic products having smaller form factor, superior functionality, reduced power consumption with a lower overall cost the market is expected to witness adoption of advanced packaging technologies such as 3D TSV during the forecast period.